Publications
2024
o Journal
Kashif Inayat, Inayat Ullah and Jaeyong Chung, "Factored Systolic Arrays based on Radix-8 Multiplication for Machine Learning Acceleration", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, 2024 (accepted)
2023
o Conference
Phouc Pham and Jaeyong Chung, "AGD: A Learning-based Optimzation Framework for EDA and its Application to Gate Sizing", IEEE/ACM Proc. Design Automation Conference (DAC), July 2023
2022
o Journal
Kashif Inayat and Jaeyong Chung, "Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, 2022
2021
o Journal
Phuoc Pham, Jacob A. Abraham, and Jaeyong Chung, "Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer", IEEE Access, Vol. 9, March 2021 (code)
2020
o Journal
Inayat Ullah, Joon-Sung Yang, and Jaeyong Chung, "ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 4, April 2020
Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang. "Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits", IEEE Access, Vol. 8, September 2021
o Conference
Inayat Ullah, Kashif Inayat, Joon-Sung Yang, and Jaeyong Chung, "Factored Radix-8 Systolic Array for Tensor Processing", IEEE/ACM Proc. Design Automation Conference (DAC), July 2020
Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang, "Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture", Design Automation & Test in Europe (DATE), March 2020
2019
o Journal
Pilyeong Jeong, Mungyeong Choe, Nahyeong Kim, Jaehyun Park, and Jaeyong Chung, "Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks", IEEE Access, Vol. 7, December 2019
Woochul Kang and Jaeyong Chung, "Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices", IEEE Access, Vol. 7, December 2019
Yongshin Kang, Joon-Sung Yang, and Jaeyong Chung, "Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 11, November 2019
Jaeyong Chung, Taehwan Shin, and Joon-Sung Yang, "Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 11, November 2019
Woochul Kang and Jaeyong Chung, "DeepRT: Predictable Deep Learning Inference for Cyber-Physical Systems", Real-time Systems, Vol. 55, No. 1, January 2019
2018
o Journal
Hyunseung Han, Jaeyong Chung, and Joon-Sung Yang, "READ:Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution", IEEE Transactions on Computers (TC), Vol. 67, No. 8, August 2018
Sae-Eun Kim, Jaeyong Chung, and Joon-Sung Yang, "Mitigating Observability Loss of Toggle-based X-Masking via Scan Chain Partitioning", IEEE Transactions on Computers (TC), Vol. 67, No. 8, August 2018
2017
o Journal
Woochul Kang and Jaeyong Chung, "Energy-Efficient Response Time Management for Embedded Databases", Real-time Systems, Vol. 53, No. 2, March 2017
o Conference
Yongshin Kang, Seban Kim, Taehwan Shin, and Jaeyong Chung, “Running Convolutional Layers of AlexNet in Neuromorphic Computing System”, Proc. IEEE Design Automation & Test in Europe Conference (DATE), March 2017 (Accepted, U-booth Demo)
Seban Kim and Jaeyong Chung, “Synthesis of Activation-Parallel Convolution Structures for Neuromorphic Architectures”, Proc. IEEE Design Automation & Test in Europe Conference (DATE), March 2017 (Accepted for Presentation) (Acceptance Rate: 193/794 = 24%)
2016
o Journal
Jaeyong Chung and Woochul Kang, "Defect Diagnosis via Segment Delay Learning", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 1,January 2016
o Conference
Jaeyong Chung and Taehwan Shin, “Simplifying Deep Neural Networks for Neuromorphic Architectures”, Proc. IEEE/ACM Design Automation Conference (DAC), June 2016 (Acceptance Rate: 152/876 = 17%)
Taehwan Shin, Yongshin Kang, Seungho Yang, Seban Kim, and Jaeyong Chung, “Live Demonstration: Real-Time Image Classification on a Neuromorphic Computing System with Zero Off-Chip Memory Access”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2016
2015
o Journal
Jaeyong Chung and Jibum Kim, "Segment Delay Learning From Quantized Path Delay Measurements", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol. 34, No. 6, June 2015
Jaeyong Chung and Lok-won Kim, “Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems”,IEEE Transactions on Computers (TC), Vol. 64, No. 11, November 2015
2014
o Journal
Jaeyong Chung, Yonghyun Kim, and Joon-sung Yang, "3D Probe: Low-cost Variation Modeling Using Inter-test-item Correlations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol. 33, No. 12, December 2014
2013
o Journal
Jaeyong Chung and Jacob A. Abraham, “A Concurrent Path Selection Algorithm in Statistical Timing Analysis”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 9, September 2013
Jaeyong Chung, Joonsung Park, and Jacob A. Abraham, “A Built-In Repar Analyzer with Optimal Repair Rate for Word-Oriented Memories”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , Vol. 21, No. 2, February 2013
2012
o Journal
Jaeyong Chung and Jacob A. Abraham, “On Computing Criticality in Refactored Graphs”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol. 31, No. 12, December 2012
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham, “Testability Driven Statistical Path Selection” , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 8, August 2012
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham, “Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 4, April 2012
Jaeyong Chung and Jacob A. Abraham, “Refactoring of Timing Graphs and its Use in Capturing Topological Correlation in SSTA”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 4, April 2012
2011
o Journal
Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh and Jacob A. Abraham, “Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, No 4, May 2011
o Conference
Eun Jung Jang, Jaeyong Chung, and Jacob A. Abraham, “ Delay Defect Diagnosis using Path Delay Measurements ”, Proc. IEEE International Symposium Integrated Circuit (ISIC), December 2011
Eun Jung Jang, Jaeyong Chung, Anne Gattiker, Sani Nassif and Jacob A. Abraham, “ Post-Silicon Timing Validation Method using Path Delay Measurements ”, Proc. IEEE Asian Test Symposium (ATS), November 2011 (Selected in the ATS 20th anniversary compendium)
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham, “Testability Driven Statistical Path Selection” , Proc. IEEE/ACM Design Automation Conference (DAC), 2011
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham, “Path Criticality Computation in Parameterized Statistical Timing Analysis”,Proc. IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), 2011 (Nominated for Best Paper Award)
2010
o Conference
Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, and Jacob A. Abraham, “At-speed Test of High-Speed DUT Using Built-off Test Interface”, Proc. IEEE Asian Test Symposium (ATS), December, 2010
Hyunjin Kim, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, and Jacob A. Abraham, “A Built-In Self Test Scheme for High Speed I/O Using Cycle-by-cycle Edge Control”, Proc. IEEE European Test Symposium (ETS), May, 2010
Jaeyong Chung, Joonsung Park, Eonjo Byun, Cheol-Jong Woo, and Jacob A. Abraham, “Reducing Test Time and Area Overhead of an Embedded Memory Array Built-In Repair Analyzer with Optimal Repair Rate”, Proc. IEEE VLSI Test Symposium (VTS), April, 2010
2009
o Conference
Joonsung Park, Jaeyong Chung, and Jacob A. Abraham, “LFSR-based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits”, Proc. IEEE Asian Test Symposium (ATS), November, 2009
Jaeyong Chung and Jacob A. Abraham, “A Hierarchy of Subgraphs Underlying a Timing Graph and its Use in Capturing Topological Correlation in SSTA”, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD), November, 2009 (Nominated for Best Paper Award)
Jaeyong Chung and Jacob A. Abraham, “Recursive Path Selection for Delay Fault Testing”, Proc. IEEE VLSI Test Symposium (VTS), May, 2009