Publications

Selected publications from HAI Lab

2026

Journals

Variation Resilient Schemes and Approximation-Free Offset Compensation for Reliable ReRAM-based DNN Accelerators
J.-W. Jang, J. Oh, S.-H. Cho, J.-Y. Hong, M. Imran, Jaeyong Chung and J.-S. Yang
IEEE Transactions on Emerging Topics in Computing (TETC) SCI Q1HW Design

2025

Conferences

DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Insu Choi, Jaeyong Chung, and Joon-Sung Yang
IEEE/ACM Proc. Design Automation Conference (DAC), July Top-tierHW Design

Journals

AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing
Phouc Pham, Taemin Park, Sunghyuk Cho, Taeyyeb Mahmood, Joon-Sung Yang, and Jaeyong Chung
ACM Transactions on Design Automation of Electronic Systems (TODAES) Top-tierAX/EDA
Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach
Jae-Youn Hong, Je-Woo Jang, Sung-Hyuk Cho, Youngbae Kong, Sungkyu Kim, Youngjung Kang, Jaehyung Ko, Jaeyong Chung, and Joon-Sung Yang
Journal of Systems Architecture (JSA) SCI Q1HW Design

2024

Journals

FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach
Kashif Inayat, Fahad Bin Muslim, Tayyeb Mahmood, and Jaeyong Chung
Journal of Systems Architecture (JSA) SCI Q1AX/EDA
Factored Systolic Arrays based on Radix-8 Multiplication for Machine Learning Acceleration
Kashif Inayat, Inayat Ullah and Jaeyong Chung
IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol 32, No. 7, July Top-tierHW Design (TVLSI Spotlight Article)

2023

Conferences

AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing
Phouc Pham and Jaeyong Chung
IEEE/ACM Proc. Design Automation Conference (DAC), July Top-tierAX/EDA

2022

Journals

Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration
Kashif Inayat and Jaeyong Chung
IEEE Transaction on Very Large Scale Integration (VLSI) Systems Top-tierHW Design

2021

Journals

Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer
Phuoc Pham, Jacob A. Abraham, and Jaeyong Chung
IEEE Access, Vol. 9, March SCIAI

2020

Conferences

Factored Radix-8 Systolic Array for Tensor Processing
Inayat Ullah, Kashif Inayat, Joon-Sung Yang, and Jaeyong Chung
IEEE/ACM Proc. Design Automation Conference (DAC), July Top-tierHW Design
Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture
Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang
Design Automation & Test in Europe (DATE), March HW Design

Journals

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
Inayat Ullah, Joon-Sung Yang, and Jaeyong Chung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 4, April Top-tierHW Design
Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits
Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang
IEEE Access, Vol. 8, September SCIHW Design

2019

Journals

Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks
Pilyeong Jeong, Mungyeong Choe, Nahyeong Kim, Jaehyun Park, and Jaeyong Chung
IEEE Access, Vol. 7, December SCIAI
Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices
Woochul Kang and Jaeyong Chung
IEEE Access, Vol. 7, December SCIAI
Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems
Yongshin Kang, Joon-Sung Yang, and Jaeyong Chung
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 11, November Top-tierAI
Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems
Jaeyong Chung, Taehwan Shin, and Joon-Sung Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 11, November Top-tierAI
DeepRT: Predictable Deep Learning Inference for Cyber-Physical Systems
Woochul Kang and Jaeyong Chung
Real-time Systems, Vol. 55, No. 1, January SCIAI

2018

Journals

READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution
Hyunseung Han, Jaeyong Chung, and Joon-Sung Yang
IEEE Transactions on Computers (TC), Vol. 67, No. 8, August Top-tierHW Design
Mitigating Observability Loss of Toggle-based X-Masking via Scan Chain Partitioning
Sae-Eun Kim, Jaeyong Chung, and Joon-Sung Yang
IEEE Transactions on Computers (TC), Vol. 67, No. 8, August Top-tierHW Design

2017

Conferences

Running Convolutional Layers of AlexNet in Neuromorphic Computing System
Yongshin Kang, Seban Kim, Taehwan Shin, and Jaeyong Chung
Proc. IEEE Design Automation & Test in Europe Conference (DATE), March AI
Synthesis of Activation-Parallel Convolution Structures for Neuromorphic Architectures
Seban Kim and Jaeyong Chung
Proc. IEEE Design Automation & Test in Europe Conference (DATE), March AI

Journals

Energy-Efficient Response Time Management for Embedded Databases
Woochul Kang and Jaeyong Chung
Real-time Systems, Vol. 53, No. 2, March SCIHW Design

2016

Conferences

Simplifying Deep Neural Networks for Neuromorphic Architectures
Jaeyong Chung and Taehwan Shin
Proc. IEEE/ACM Design Automation Conference (DAC), June Top-tierAI
Live Demonstration: Real-Time Image Classification on a Neuromorphic Computing System with Zero Off-Chip Memory Access
Taehwan Shin, Yongshin Kang, Seungho Yang, Seban Kim, and Jaeyong Chung
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May HW Design

Journals

Defect Diagnosis via Segment Delay Learning
Jaeyong Chung and Woochul Kang
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 1, January Top-tierAX/EDA

2015

Journals

Segment Delay Learning From Quantized Path Delay Measurements
Jaeyong Chung and Jibum Kim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 6, June Top-tierAX/EDA
Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems
Jaeyong Chung and Lok-won Kim
IEEE Transactions on Computers (TC), Vol. 64, No. 11, November Top-tierAX/EDA

2014

Journals

3D Probe: Low-cost Variation Modeling Using Inter-test-item Correlations
Jaeyong Chung, Yonghyun Kim, and Joon-sung Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 12, December Top-tierAX/EDA

2013

Journals

A Concurrent Path Selection Algorithm in Statistical Timing Analysis
Jaeyong Chung and Jacob A. Abraham
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 9, September Top-tierAX/EDA
A Built-In Repair Analyzer with Optimal Repair Rate for Word-Oriented Memories
Jaeyong Chung, Joonsung Park, and Jacob A. Abraham
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 2, February Top-tierHW Design

2012

Journals

On Computing Criticality in Refactored Graphs
Jaeyong Chung and Jacob A. Abraham
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 12, December Top-tierAX/EDA
Testability Driven Statistical Path Selection
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 8, August Top-tierAX/EDA
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 4, April Top-tierAX/EDA
Refactoring of Timing Graphs and its Use in Capturing Topological Correlation in SSTA
Jaeyong Chung and Jacob A. Abraham
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 4, April Top-tierAX/EDA

2011

Conferences

Testability Driven Statistical Path Selection
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham
Proc. IEEE/ACM Design Automation Conference (DAC) Top-tierAX/EDA
Path Criticality Computation in Parameterized Statistical Timing Analysis
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, and Jacob A. Abraham
Proc. IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC) AX/EDA (Nominated for Best Paper Award)
Post-Silicon Timing Validation Method using Path Delay Measurements
Eun Jung Jang, Jaeyong Chung, Anne Gattiker, Sani Nassif and Jacob A. Abraham
Proc. IEEE Asian Test Symposium (ATS), November AX/EDA (Selected in the ATS 20th anniversary compendium)
Delay Defect Diagnosis using Path Delay Measurements
Eun Jung Jang, Jaeyong Chung, and Jacob A. Abraham
Proc. IEEE International Symposium Integrated Circuit (ISIC), December AX/EDA

Journals

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip
Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh and Jacob A. Abraham
Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, No 4, May SCIHW Design

2010

Conferences

At-speed Test of High-Speed DUT Using Built-off Test Interface
Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, and Jacob A. Abraham
Proc. IEEE Asian Test Symposium (ATS), December HW Design
A Built-In Self Test Scheme for High Speed I/O Using Cycle-by-cycle Edge Control
Hyunjin Kim, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, and Jacob A. Abraham
Proc. IEEE European Test Symposium (ETS), May HW Design
Reducing Test Time and Area Overhead of an Embedded Memory Array Built-In Repair Analyzer with Optimal Repair Rate
Jaeyong Chung, Joonsung Park, Eonjo Byun, Cheol-Jong Woo, and Jacob A. Abraham
Proc. IEEE VLSI Test Symposium (VTS), April Top-tierHW Design

2009

Conferences

A Hierarchy of Subgraphs Underlying a Timing Graph and its Use in Capturing Topological Correlation in SSTA
Jaeyong Chung and Jacob A. Abraham
Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD), November Top-tierAX/EDA (Nominated for Best Paper Award)
LFSR-based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits
Joonsung Park, Jaeyong Chung, and Jacob A. Abraham
Proc. IEEE Asian Test Symposium (ATS), November HW Design
Recursive Path Selection for Delay Fault Testing
Jaeyong Chung and Jacob A. Abraham
Proc. IEEE VLSI Test Symposium (VTS), May Top-tierAX/EDA